The continued proliferation of mixed analog/digital VLSI systems demands new design techniques for mixed-mode integrated circuits. While a conventional static CMOS logic gate has many desirable properties, its primary problem for high-speed, high-performance mixed-mode ICs is the generation of a very large current spike (typically several mA per gate per transition) during the transition between states. In a typical VLSI circuit, hundreds or thousands of logic gates may switch states simultaneously. The resulting current pulses can generate substantially large switching noise and voltage drops on the power supply lines due to the IR and LdI/dt effects. For mixed-mode VLSI systems where the analog and digital circuitry share a common substrate and possibly common power lines, the digital switching noise inevitably couples into the analog circuitry degrading its accuracy, especially at higher frequencies.
In general, there are two different sources of extrinsic noise in a CMOS VLSI chip. The first is an induced noise appearing at a particular node in the circuit which is coupled (usually capacitively) from adjacent nodes. The other source of noise is due to the resistive and inductive effects of current spikes which are generated during the transitions of logic gates, and which are coupled globally to other circuitry via the common substrate and via radiation.
As large digital systems change states, large numbers of gates make transitions which generate very large current spikes. (See, for example, J. A. Olmstead, "Noise Problems in Mixed A/D ICs," Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 659-662, 1986.) Since one of the power supply lines is usually connected to the common substrate of the CMOS IC (i.e., V.sub.cc if p-well CMOS, and GND if n-well CMOS), this noise is propagated through the substrate to all of the circuitry on the chip. The noise pollution associated with this power bus noise can significantly degrade the accuracy of analog circuits which share the same substrate.
Several methods have been proposed for reducing the effects of power bus noise. These including filtering the power busses using on-chip active filters and active guardbanding to increase the isolation between separate analog and digital circuitry on the same IC. However, none of these approaches has proved fully satisfactory.
In accordance with the present invention, switching current transients in mixed mode circuitry are greatly minimized by use of source-coupled differential CMOS logic circuits that steer a fixed current from one side of a differential topology to another depending on the applied input voltage. The circuitry can also feature a logic swing of about 500-800 millivolts, which results in substantial reduction in propagation delay, reactive power dissipation, and further reduction in the switching current spike. In the preferred embodiment, gain and level shifting stages are merged, resulting in still smaller current transients, lower power consumption, and higher speed.
The foregoing and additional features and advantages of the invention will be more readily apparent from the following detailed description, which proceeds with reference to the accompanying drawings.